FPGA Engineer

Vivid Resourcing is looking for a Senior FPGA Engineer for an expanding hardware development team of our client. The role involves supporting the development of high-speed sensor data acquisition systems and dedicated multi-gigabit communication links. This is a 12-month freelance opportunity for an experienced FPGA engineer who can become productive quickly and work independently within an established architecture. You will take ownership of RTL implementation, I/O and data paths, with a strong focus on timing, latency and reliable cross-domain behaviour.

The initial requirement is for 1-2 engineers, with an ASAP start or within one month. The role is based in Overijssel, with two days per week on-site.

Main responsibilities include: designing and implementing FPGA functionality using RTL; working with Intel/Altera FPGAs, ideally the Agilex family; developing and maintaining high-speed transceiver functionality and multi-gigabit communication links; working with transceiver speeds from approximately 12.5 Gbps upwards; designing timing-critical RTL operating at 200 MHz and above; monitoring and optimising latency across the data path; supporting sensor data acquisition and the transfer of data to a central system; developing and maintaining SPI interfaces, including interfaces to ADCs; debugging timing, clock-domain crossing and other FPGA-related issues; supporting FPGA I/O and interface control; contributing to architecture and specification discussions where required; and working independently within an established architecture and delivering with limited ramp-up time.

Requirements include: several years of senior, hands-on FPGA engineering experience; strong experience working with high-speed FPGA transceivers; experience with Intel/Altera FPGAs, ideally Agilex; proven experience with multi-gigabit communication links, ideally at 12.5 Gbps or above; strong RTL design experience; experience designing and achieving timing closure on FPGA designs operating at 200 MHz or above; strong understanding of clock-domain crossing and timing challenges; experience working with latency-sensitive data paths; experience with SPI and ADC interfaces; ability to read and understand hardware architecture and work closely with hardware engineers; comfort working independently and becoming productive quickly; and professional working proficiency in English.

The offer includes a 12-month freelance contract, ASAP start or within one month, 2 days per week on-site in Overijssel, an opportunity to work on high-speed sensor data acquisition and multi-gigabit communication technology, a senior-level position within an expanding hardware development team, and an initial requirement for 1-2 engineers. The strongest candidates will bring a genuinely senior FPGA background, particularly around high-speed transceivers, multi-gigabit data links and timing-critical RTL.

Experience with Agilex or comparable Intel/Altera devices will be particularly relevant. This role is less focused on advanced DSP or complex control-loop development. The core challenge is bringing together high-speed transceivers, robust RTL, timing closure, latency, I/O and sensor data acquisition within an established architecture.